Forum Discussion

MEmel1's avatar
MEmel1
Icon for New Contributor rankNew Contributor
6 years ago

How can I initiate burst transfer for Avalon-MM in EMIF Cyclone 10?

Hello, My problem is that the component altera_emif_c10 (DDR3) doesn't complete reads with burstcount[..] set to more than 1. According to Avalon-MM interface protocol burst writes and reads are co...
NurAida_A_Intel's avatar
NurAida_A_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Dear MEmel1,

Please accept my apology for the delay in response due to recent workload.

Actually the parameter is hidden in the altera_emif_c10 GUI. You can go to your top right of the GUI (beside Generate Example Design tab) --> right click --> click show hidden parameter and you should be able to see the parameter of max burst length in the GUI.

Also, you may refer to this Cyclone 10 EMIF user guide for more info --> https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20116.pdf

Hope this helps. Feel free to let me know if you have any concern.

Again I sincerely apologize for the delay in response.

Thanks

Regards,

NAli1

MEmel1's avatar
MEmel1
Icon for New Contributor rankNew Contributor
6 years ago

Hello, NAli1,

Thank you for your answer!

I managed to find maximum burst length parameter in hidden parameters. It's set to 4. So theoretically everything should have been working already..

But what about burstbegin signal? How burst write/read should be initiated without burstbegin signal?

Thanks