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abhishek's avatar
abhishek
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7 years ago

hi i have generated the esram ip from ip catalog and am trying to simulate the ip but am unable to get the output clock and locked signal

can anyone help me out with this

4 Replies

  • AnandRaj_S_Intel's avatar
    AnandRaj_S_Intel
    Icon for Regular Contributor rankRegular Contributor
    7 years ago

    Hi,

    Can you share more information?

    Version of tools and Full name of the IP used in you design with simulation images.

    If possible do share project files.

    Regards

    Anand

    • abhishek's avatar
      abhishek
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      7 years ago

      Hi Raj

      am using 18.1 quartus tool and IP name is "ESRAM" here am attaching the project files and the simulation waveform capture,while generating the IP core i configured the 'refclk' as 100Mhz and output clk as 500Mhz but when am trying to drive the reflck from the testbbench am able to get the refernce clk but am unable to generate the output core clk and lock signal , is there anything i have to drive from the testbench??

      Abhishek

    • abhishek's avatar
      abhishek
      Icon for New Contributor rankNew Contributor
      7 years ago

      hi few points to add

      am using stratix 10 MX board

    • abhishek's avatar
      abhishek
      Icon for New Contributor rankNew Contributor
      7 years ago

      Hi Raj is there any updated info regarding the "esram ipcore" ,we need simulation to be tested for our further integration.Could you please give me some info regarding the issue ASAP.

      Regards

      Abhishek