If your fft functional simulation is ok and your timing report is ok then we can forget about timing. I will check these issues:
1) is your analogue input not fluctuating. can you exclude that by inputting from a LUT as a test.
2) is your data representation from ADC correct. Some ADCs use 2's complement, others use offset binary. They are different of course.
3) is your scaling correct. This is the most likely culprit for now. Remember altera has left scaling algorithm to the designer. make sure you are scaling each block correctly and not latching the exponent from block to block.
4) is there any clipping/overflow of data, though clipping will lead to widening of spectrum side lobes, overflow and unwrapping will lead to spikes on either side of your sine point.