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JShel4
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7 years ago

Help with A10 Backplane Auto Negotiation

Hello, I need help/pointers for debug of Backplane Auto Negotiation. My System: Arria10 FPGA <=> Copper Backplane <=> AMD SoC Both partners are capable of 10G and 1G modes I have matched the ...
JShel4's avatar
JShel4
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7 years ago

Hi Chee Pin,

In the XCVR PHY User Guide: 2.6.3. 10GBASE-KR PHY IP Core This is the IP I am using for 10g Backplane interface (1-lane).

Those signals are inside the IP -- not the signals/interfaces available at top level to a user

If you go down to the level where Sequencer is instantiated, you will see those signals.

Thanks!