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JShel4's avatar
JShel4
Icon for New Contributor rankNew Contributor
6 years ago

Help with A10 Backplane Auto Negotiation

Hello, I need help/pointers for debug of Backplane Auto Negotiation. My System: Arria10 FPGA <=> Copper Backplane <=> AMD SoC Both partners are capable of 10G and 1G modes I have matched the ...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
6 years ago
Hi Jaydev, Thanks for your clarification. Just would like to double check with you if you are using 10GBASE-KR PHY IP Core or 1-Gigabit/10-Gigabit Ethernet (GbE) PHY IP Core as described in the A10 XCVR PHY user guide? If not, please feel free to refer me to the specific web link or documentation reference for it. This would be helpful for me to debug into the right IP. Sorry for the inconvenience. The reason I am asking this is because I am unable to find an_rx_idle or an_pg_received status signals at the above PHY IP core. Thank you. Best regards, Chee Pin