Forum Discussion
JShel4
New Contributor
New ContributorHelp with A10 Backplane Auto Negotiation
Hello, I need help/pointers for debug of Backplane Auto Negotiation. My System: Arria10 FPGA <=> Copper Backplane <=> AMD SoC Both partners are capable of 10G and 1G modes I have matched the ...
JShel4New Contributor
New ContributorHello,
Yes, I am using the 1G/10G Ethernet IP in Arria10.
My observation:
- FPGA believes to be sending the right DME -- I can see it in SignalTap
- But, I don't see the AMD registering that information -- I see this by reading the LP registers using the MDIO interface
- The same happens in reverse direction:
- i.e. AMD believes it is sending information (again, I read the advertised/tech registers using MDIO interface) ...
- but, FPGA is not registering these values in the LP registers ... actually, I don't even see the page_received signal go high.
Please share any tips/tricks/information you may have with Arria10 experience. Thank You very much in advance!
