HDMI compliance issue

HI Jay,

Pls see my comment below.

1. When the video source has larger jitter...

• This is a very subjective question and literally depend on your actual design implementation (timing constraint, fitter placement, which PLL location usage and etc)
  • Anyway, you can refer to A10 datasheet table 38 and table 39 for A10 fPLL and IOPLL spec guideline
    • https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/a10_datasheet.pdf
    • Do take note of NOTE65 : A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps.

1. The fPLL is set to "CASCADE SOURCE" in FPLL MODE in Platform Designer...

• I reviewed A10 HDMI reference design and I can see that it's using PLL cascade mode as well. The only difference is the reference design is using IOPLL instead of fPLL.
  • You can take a look of the reference design as well. checkout hdmi_rx_top.v design file in <project>\ip\hdmi_subsys\hdmi_subsys_alt_hdmi_example_design\alt_hdmi_example_design\rtl\hdmi_rx
  • https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an776.pdf

Thanks.

Regards,

dlim