Forum Discussion
JWang21
New Contributor
6 years agoHDMI compliance issue
Currently our design (using 10AX115) is suffering a HDMI compatibility issue with a certain video source. The HDMI Rx is Coretronix's in-house IP. The Tx is a specific video box. We already know tha...
JWang21
New Contributor
6 years agoHi Dlim,
Do you have any comment for these 2 condition,
1) When the video source has larger jitter, the fPLL can still lock to the incoming TMDS clock, though the data seems to be incorrectly decoded as the Rx fails to sync with Tx.
2) The fPLL is set to "CASCADE SOURCE" in FPLL MODE in Platform Designer. The fPLL's output is used as the XCVR's CDR reference clock. It does not connect to other fPLL or ATXPLL.
Thanks,
Jay