Forum Discussion
New ContributorGPIO DDRIO IP output swapped: datainhi/datainlo inverts forwarded clock
Hello Paul,
We have checked the design. We think it may be because of your coding design. We switched your 10 to 01 and got this result. Is this what you are expecting?
Image 1: Waveform
Image 2: Design
Image 3: Reference from https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_gpio.pdf
Thank you.
New ContributorThe synthesized design behaves as the simulation shows: the signal on datainhi is output on the falling edge of the clock. For my source synchronous interface, this was sneaking in a 180-degree phase shift on the output clock. The timing analyzer assumes pos-unate edges so data transitions occur in the wrong place relative to the active edge of the clock, which breaks my interface. If I swap datainhi and datainlo, my design works as expected.
Regular ContributorHello Paul,
We have checked the design. We think it may be because of your coding design. We switched your 10 to 01 and got this result. Is this what you are expecting?
Image 1: Waveform
Image 2: Design
Image 3: Reference from https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_gpio.pdf
Thank you.
- pnp
Amin,
Thank you for looking into this issue! That is exactly where I ended up: I swapped the din values as you did. I see the waveform you posted from the documentation, but that is for half-rate conversion. We are not doing half-rate conversion in this case.
My issue is that the behavior contradicts the documentation:
from https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_gpio.pdf
In this case, datain_width is 1. So
datain_h = din[(2 * 1 - 1):1] = din[1:1] and
datain_l = din[(1 - 1):0] = din[0:0]
which matches what I see in the technology mapped netlist (see my initial post in this issue). The comment at the end of the document states:
which is what I expect to happen, however swapping values in din is required to get the expected behavior.
Thanks,
Paul
- AminT_Intel
Hello,
The last screenshot you've given is on Guideline: Swap datain_h and datain_l Ports in Migrated IP which is for migration for your GPIO IP from previous devices to the GPIO IP core. This only applies only for the migration.
- pnp
Amin,
I am grateful for your assistance in resolving this issue: all of our cyclone10gx_ddio_out instances are working properly now in our FPGA design. I accept that I have misunderstood the documentation and that the GPIO IP is working as Altera designed. I'd suggest, though, that it would be helpful if someone added a full-rate scenario timing diagram to the docs, because the IP does behave differently than the legacy altddio_out megafunction with nearly identical port names. At the very least, this thread will be here if anyone else is snagged.
Best regards,
Paul
