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Now the question is you are interpolating from 176.4KHz to 100MHz. The ratio is fractional and so you need to do fractional interpolation.
Alternatively set DAC to multiple of 176.4KHz
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Actually it is not 176.4 KHz... I changed it later to be multiple of 100 MHz and forgot :P It's 178.571 KHz
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There is also issue of using different clock rates on FIR and CIC. Do you need that. You better use same system clock or it may go wrong
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I thought I have to clock the CIC with the required output sampling rate, that is 10 MHz.
Actually, after the succes I got in SignalTap, I went back to ModelSim to simulate the design as is. But I got a totally different and strange output:
http://www.alteraforum.com/forum/attachment.php?attachmentid=10282&stc=1 I tried to use same system clock for both IPs as you mentioned... nothing changed except the output of FIR was distorted and CIC gave exactly the same
output of FIR.
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