FIR and CIC MegaCores Altogether

Honored Contributor

11 years ago

I changed the CIC clock to 10 MHz, it was 100 MHz... output of FIR is around 1.42 MSPS and interpolation factor is 7.

And this is my configuration:

In SignalTap I got this:

You can see that CIC is producing samples like bursts (dout and out_valid signals)

And it is accepting samples all the time (RRC: ast_source_ready signal)

RRC is driving its output_ready signal along with CIC's out_valid. (This is strange)

I used edge detector to drive CIC's in_valid signal.

All that resulted in this:

After deleting samples that aren't associated with validity signal... I got this:

Which I need to have as a direct output of the CIC.

I feel that outputs of FIR and CIC should be swapped... I mean FIR must provide data as bursts

and CIC must spite out samples continuously.

I think there is something to do with what you've just mentioned... don't you think that Back Pressure should handle this? It's enabled!

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