FIR and CIC MegaCores Altogether

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I do have it... but I can't simulate it... however, I used SignalTap to observe the output... it was distorted.

I connected "in_ready" output signal of CIC to the input "ast_source_ready" of FIR. I don't think there is much to do. Or is there?

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when cic is ready for input the fir will then produce ouput late due to FIR latency.

You need to have CIC input ready when it asks for it. I think a fifo will do. write to fifo FIR output on valid out and read fifo on CIC in_ready with enough fifo depth.