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TMK
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7 years ago

FIFOed UART Qsys Generation Error with Qsys Standard v18.1

Hello, when generating a FIFOed UART with Qsys Standard v18.1 as provided here https://forums.intel.com/s/createarticlepage?language=en_US&articleid=a3g0P0000005RTHQA2&artTopicId=0TO0P000000MWKBWA4...
TMK's avatar
TMK
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7 years ago

Thank you for your update. In order to reproduce the issue you have to select "Create simulation model: VHDL" in the generation window. Could you please try that as well?