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TMK's avatar
TMK
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6 years ago

FIFOed UART Qsys Generation Error with Qsys Standard v18.1

Hello, when generating a FIFOed UART with Qsys Standard v18.1 as provided here https://forums.intel.com/s/createarticlepage?language=en_US&articleid=a3g0P0000005RTHQA2&artTopicId=0TO0P000000MWKBWA4...
KennyT_altera's avatar
KennyT_altera
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6 years ago

may I know what OS that you were using? I will try duplicate it and find the workaround for it.

  • TMK's avatar
    TMK
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    6 years ago

    I'm using Windows 7. Important information is that the problem only happens when generating VHDL (not Verilog) output and seems to be related to the synthesis directive.