Forum Discussion
New ContributorFIFO Intel FPGA IP (DCFIFO) with clock that is not continuous
Hi,
Consider that you have a DCFIFO which has continuous rdclk but wrclk comes in only with the data, i.e. one clock per data.
The problem with this type of write clocking is that you need at least one extra clock to read the last data. Reason is this setting for DCFIFO:
Minimal setting for unsynchronized clocks This option uses two synchronization stages with good metastability protection. It uses the medium size and provides good fMAX. This needs an extra clock to compensate for the two synchronization stage.
Similar thing if the FIFO has continuous wrclk but sparse rdclk.
To understand it better, you may run simulations before implementing it on board.
Regards
Regular ContributorHi,
Consider that you have a DCFIFO which has continuous rdclk but wrclk comes in only with the data, i.e. one clock per data.
The problem with this type of write clocking is that you need at least one extra clock to read the last data. Reason is this setting for DCFIFO:
| Minimal setting for unsynchronized clocks | This option uses two synchronization stages with good metastability protection. It uses the medium size and provides good fMAX. |
This needs an extra clock to compensate for the two synchronization stage.
Similar thing if the FIFO has continuous wrclk but sparse rdclk.
To understand it better, you may run simulations before implementing it on board.
Regards
