Forum Discussion
Altera_Forum
Honored Contributor
12 years agoHello, sorry for the late feedback. Did you solve your problem ?
I tried with your file, and it did not work. Then I tried to generate myself the files with the megawizard in verilog, it still did not work. Using the fft_tb.v, fft_bb.v and fft.vo files, i have the following warning when I start the simulation, I don't if this can be the origin of the problem : # ** Warning: (vsim-3009) [TSCALE] - Module 'fft' does not have a `timescale directive in effect, but previous modules do. # Region: /fft_tb/dut Then I tried to generate myself the files with the megawizard in VHDL, and here it worked (and here I effectively need only the test bench and the fft.vho files, but not the fft.vhd file). I never used verilog, so I don't know if some special things are needed compared to the VHDL. Sorry to not be able to help more. As a remark, the fft_bb file is not generated when we select vhdl, this is why I was surprised about this file (and because it is not mentioned in the documentation).