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Altera_Forum's avatar
Altera_Forum
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17 years ago

FFT Mega Core IP

I am working on FFT MegaCore IP. I would like to give 64 points to the generated file and get the output using Altera DE2 board not the simulation. I built a top level file.v to pass the inputs...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

hello,

i'm a bit busy at work lately and Verilog is not my native tongue. :)

source_ready and sink_valid look like they should be correct. is there anything on the source_error outputs?

do you have ModelSim waveforms?