Forum Discussion

zjj's avatar
zjj
Icon for Occasional Contributor rankOccasional Contributor
2 months ago
Solved

F-tile ethernet hard ip in agilex7

I generate 200G ethernet F-tile hard ip that base on agilex7, the IP configuration as follow: Our current test setup uses our custom development boards interconnected with Mellanox CX-8....
Ethernet
  • paveetirrasrie_Altera's avatar
    paveetirrasrie_Altera
    1 month ago

    Hello,

     

    The recommended workaround is to re-apply the TX pause configuration in software after hot-plug/link recovery. In practice, after the optical module is reinserted and the link comes back up, rewrite TX_PAUSE_EN (tx_pause_en, offset 0x122C[8:0]) because that register controls the TX PAUSE / TX PFC enable bits and can end up cleared.

     

    Regards,

    Pavee

zjj's avatar
zjj
Icon for Occasional Contributor rankOccasional Contributor
1 month ago

During on-board debugging of the F-tile MAC Hard IP, we observed that the TX_PAUSE_EN register is automatically cleared to 0 after the optical module is hot-plugged (when the link goes down and then comes back up). What is the recommended workaround for this issue?

 

  • paveetirrasrie_Altera's avatar
    paveetirrasrie_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    1 month ago

    Hello,

     

    The recommended workaround is to re-apply the TX pause configuration in software after hot-plug/link recovery. In practice, after the optical module is reinserted and the link comes back up, rewrite TX_PAUSE_EN (tx_pause_en, offset 0x122C[8:0]) because that register controls the TX PAUSE / TX PFC enable bits and can end up cleared.

     

    Regards,

    Pavee