Forum Discussion
Error(332000)
Can you describe what you were doing to get this error? Is it repeatable?
- ymiler5 years ago
Contributor
Yes ,
Its repeatable - I am stuck , I can't generate FPGA version
My change was defintion on the LVDS SERDES IP GUI - get clock from external PLL instead of internal PLL
Yishay
- sstrell5 years ago
Super Contributor
So you're trying to (re)generate the IP in the IP Parameter Editor? Need to be more specific of exactly what you are doing and when the error occurs.
Can you show a screenshot? Are there any errors in the messages at the bottom of the IP Parameter Editor before you generate the IP, possibly indicating that you have incompatible parameters selected?
Can you try creating a brand new instance of the IP to see if the error still occurs?
And what is your Quartus version and target device?
Lots of basic info needed here to figure out what's going on.
- ymiler5 years ago
Contributor
Hi
The error occure in the middle of plan stage
Attach screenshot :
Quartos version 20.3
My target device :
I have the LVDS SERDES IP in my project -My change was defintion in the IP GUI to get clock from external PLL instead of internal PLL
There are no errors/warnings in the GUI editor when I try to regenerae
Attached screenshot :
BR
Yishay