Forum Discussion

New Contributor

4 years ago

Error when generating DDR3 Uniphy IP for Cyclone V SoC

Hello, I am getting the attached error when generating DDR3 Uniphy IP. I didn't happen on version 13.0 but happened on 14.1 and 18.1 Any advice on this issue is appreciated.. Thanks, mza...

AdzimZM_Altera

Regular Contributor

4 years ago

Hi mzan,

Have you tried the resolution from the KDBs below?

https://www.intel.com/content/www/us/en/support/programmable/articles/000080619.html

https://www.intel.com/content/www/us/en/support/programmable/articles/000086910.html

Please let me know if that help you.

Thanks,

Adzim

Forum Discussion

Error when generating DDR3 Uniphy IP for Cyclone V SoC

Recent Discussions

Cyclone IV GX PCIe Hard IP behaves differently on Intel Core I7 vs Xeon root complexes

VVP Protocol Converter Not work

mipi csi2 tx, upper limit of video width

Cyclone 10 GX transceiver register map

LVDS Output of FPGA