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pkat's avatar
pkat
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5 years ago

Ensuring synchronizer with a static flip-flop in Cyclone 10 Gx

Hello, In Cyclone 10 Gx FPGA how do I make sure that the HDL synchronizer design will synthesize using Static flip-flops instead of dynamic flip-flops? By Static flip-flop I am referring to flip-fl...
pkat's avatar
pkat
Icon for New Contributor rankNew Contributor
5 years ago

Hello,

Please see the following link for description on Dynamic Flip-flop

•https://web.stanford.edu/class/ee183/handouts/synchronization_pres.pdf

I do not know of any option within Quartus to choose the type of FF and therefore I posted the original question wondering if I can constrain on FFs so that only static FFs are chosen for synchronizer design.

Thanks

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
5 years ago

No, there are not different kinds of flip-flops like this. The Quartus Prime software can identify synchronizer chains and place and route the registers to maximize MTBF. Some online trainings that might be helpful:

https://www.intel.com/content/www/us/en/programmable/support/training/course/odswcdcc.html

https://www.intel.com/content/www/us/en/programmable/support/training/course/odsw1113.html (older but might still be relevant to your question)

The setting in Quartus:

https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#logicops/logicops/def_analyze_metastability.htm