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Occasional ContributorEMIF Cyclone 10 GX: emif_usr_clk frequency incorrect
In the top.sdc you are setting pll reference clock as 50Mhz and this causes the incorrect emif_usr_clk frequency. Please remove the following constraint from sdc then you should see the correct clock frequency in the report. The pll reference clock frequency is defined in the IP sdc.
create_clock -name {clk_emif} -period 20.0 [get_ports {emif_clk_clk}]
Occasional ContributorHere it is.
ContributorHi
When I compile the design I see the emif_usr_clk is reported as 200Mhz in the clocks GUI. Can you confirm ?
- Schroeti
Yes, exactly as I logged. Sorry, I forgot to change the reference clock back away from 50MHz before generating the qar.
Would you please set the emif pll reference clock to 200MHz, then you should see the effect.
- yoichiK_altera
In the top.sdc you are setting pll reference clock as 50Mhz and this causes the incorrect emif_usr_clk frequency. Please remove the following constraint from sdc then you should see the correct clock frequency in the report. The pll reference clock frequency is defined in the IP sdc.
create_clock -name {clk_emif} -period 20.0 [get_ports {emif_clk_clk}]
- Schroeti
That's it.
Thank you!
