Forum Discussion
ContributorElectrical IDLE in Transceiver
Regular ContributorHi HPB,
As I understand it, you have some inquiries related to the tx_pma_elecidle for S10 L-Tile XCVR for non-PCIe mode. Please see my responses to your inquiries as following:
a) What is the behavior of Transceiver p/n lines when I drive tx_PMA_elecidle = 1;
[CP] The transmitter will be tri-stated when this signal is driven high.
b) Is there any specific steps involved for enabling and disabling tx_PMA_elecidle port? (I didn't find any timing diagram to handle the port in the Stratix 10 L-tile transceiver user-guide.)
[CP] No. No specific steps or timing diagram for non-PCIe mode.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
HBhat2Hi @cheepinc_Intel ,
Thank you for clarifying when tx_PMA_elecidle = 1, the transmitter will be tri-stated.
I have a requirement that the Transmitter to be in electrical IDLE for 100ns and after that the transmitter resumes its usual traffic. So, in order to keep the transmitter in electrical IDLE, should I make port tx_PMA_elecidle = 1 for 100ns, and drive the tx_PMA_elecidle = 0 afterwards?
With regards,
HPB
- CheepinC_alteraHi HPB, Yes, your understanding is correct. It is recommended for your to run simulation in Modelsim followed by hardware testing to verify your design functionality. You may start with simple XCVR design. Thank you. Best regards, Chee Pin
- HBhat2
Hi,
I need one clarification regarding below point.
a) What is the behavior of Transceiver p/n lines when I drive tx_PMA_elecidle = 1;
[CP] The transmitter will be tri-stated when this signal is driven high.
When transmitter is tri-stated, whether common mode voltage will be maintained in the transmitter line (note that I am not enabling any PIPE/PCIe related settings, instead Native PHY will be configured with PCS Direct mode)?
With regards,
HPB
- HBhat2
Hi,
Also, when Transmitter in Electrical IDLE, whether txuserclock toggling will be valid?
If the Transmitter in electrical IDLE is loopback to a receiver, In this case, receiver also provide valid rxuserclock as required to configured data rate?
With regards,
HPB
- CheepinC_alteraHi HPB, As I understand it, when the TX buffer is put to electrical idle, the output voltage should be the common mode voltage. However, I have not physically measured this in hardware, you might need to perform hardware measurement to double check on this. Sorry for the inconvenience. Best regards, Chee Pin
