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SSikk's avatar
SSikk
Icon for New Contributor rankNew Contributor
5 years ago

E-Tile Hard IP for Ethernet Intel FPGA IP in Quartus 19.3 tool for Stratix 10-DX Device

Our design is integrated with P-Tile PCIe with Ethernet of Datawidth 512bits. Ethernet link is up but o_tx_ready of ethernet is toggling all the time rather than being high or low for some time. .stp...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

HI,

I don't hear back from you after my feedback suggestion.

Hopefully you are able to make good progress with your project development

For now, I am setting this case to closure.

Thanks.

Regards,

dlim