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SSikk's avatar
SSikk
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5 years ago

E-Tile Hard IP for Ethernet Intel FPGA IP in Quartus 19.3 tool for Stratix 10-DX Device

Our design is integrated with P-Tile PCIe with Ethernet of Datawidth 512bits. Ethernet link is up but o_tx_ready of ethernet is toggling all the time rather than being high or low for some time. .stp...
SSikk's avatar
SSikk
Icon for New Contributor rankNew Contributor
5 years ago

Hi,

Thanks for your support.

We tested example design thrice. tx_ready is behaving in the same way what I mentioned in my previous post.

Can you please guide us on how to isolate this issue?