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SSikk's avatar
SSikk
Icon for New Contributor rankNew Contributor
6 years ago

E-Tile Hard IP for Ethernet Intel FPGA IP in Quartus 19.3 tool for Stratix 10-DX Device

Our design is integrated with P-Tile PCIe with Ethernet of Datawidth 512bits. Ethernet link is up but o_tx_ready of ethernet is toggling all the time rather than being high or low for some time. .stp...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

HI,

It's not easy to isolate issue when your design is complex and combined both PCIe and Ethernet IP together.

My advice is perhaps you can try out new design with just Ethernet example design only. Make sure everything works first (both Quartus design and your board) then only add in PCIe design to it.

Thanks.

Regards,

dlim