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YBilg's avatar
YBilg
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6 years ago

DVI Output from Arria 10 Board

Hello guys, I work on a project that generates a test pattern and display it on a DVI monitor with Arria 10 SoC board. I am using Quartus 18.1. I used HDMI Intel Arria 10 FPGA IP Design Example as a...
BoonT_Intel's avatar
BoonT_Intel
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6 years ago

Hi @YBilg​

Regardless how the pixel being calculate.

Since you generate the ED, then what is the original hdmi_clk_in frequency that define in the timing analyzer? I generate the ED and I get 300MHz.

  • BoonT_Intel's avatar
    BoonT_Intel
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    6 years ago

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