New Contributor
Frequent ContributorHi Sir,
Since you are using the example design (ED) as a baseline, why not you follow the User Guide to generate the RX-TX re-transmit design then follow the step to remove the component for TX-only design.
I checked your HDMI/Native PHY IP setting, I found that for Native PHY, the data rate for ED is 6000 Mbps while you are using 3900Mbps. Maybe as a quick check, you can try to change the data rate to 6000 Mbps and try.
I summarize the suggestion as below:
1. Change the transceiver data rate to 6000 Mbps.
2. Generate the Tx-Rx design, remove the RX and other components as stated in UG. Integrate the customer video source and try.
3. If your board has the Rx channel, build the Rx-Tx design, connect Rx from external video source see it can re-transmit the video.
4. Connect the reset signal to a toggling button or ISSNP. So that you can toggle it when connecting to a monitor see if the display works after reset.
5. Upgrade the design to latest version, at least 19.4.
Last thing is how you determine the dmi_clk_in is 65Mhz? I generate the example design target Arria 10 development kit, the frequency is 300MHz.
New ContributorHello @BoonT_Intel ,
Thank you for your attention. I have tried 6000 Mbps for transceiver data rate and it didnt work. I haven't tried the Tx-Rx Design but my design is the version of removed RX and unnecessary components as explained in the user guide. In the user guide it says that the frequency of the hdmi_clk_in signal should be the same as TMDS Clock frequency. I have checked the internet for the pixel clock of the resolution 1024x768/60fps and it is 65 MHz. I thought it is also the TMDS Clock Frequency. Am I wrong about that?
