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RamaMohan's avatar
RamaMohan
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7 years ago

Does wr_dma interface of AVMM DMA descriptor controller support pipelined reads from application interface in A10

Hi, We have a use case where we wanted to use the Descriptor controller of A10 AVMM DMA with pipelined accesses on Write DMA Avalon-MM Master port. Actually we need a huge delay to respond with the ...
RamaMohan's avatar
RamaMohan
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Hi GNg,

I'm sorry for the confusion. The delay is required for the read-transactions from Read data mover to application, where data is moved from application to the system memory. We do not need any delay for the descriptor controller transaction as these are always Descriptor table writes. We don't have any specific requirement for Descriptor controller instance.

Please clarify if pipe-lining is possible for read requests from PCIe Read DMA Data Move of AVMM DMA.

Thanks,

RamaMohan