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RamaMohan's avatar
RamaMohan
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Does wr_dma interface of AVMM DMA descriptor controller support pipelined reads from application interface in A10

Hi, We have a use case where we wanted to use the Descriptor controller of A10 AVMM DMA with pipelined accesses on Write DMA Avalon-MM Master port. Actually we need a huge delay to respond with the ...
GuaBin_N_Intel's avatar
GuaBin_N_Intel
Icon for Contributor rankContributor
7 years ago

If you are using the internal descriptor controller of AVMM DMA PCIe IP, I don’t see there is an option to control the delay of descriptor controller, therefore, I afraid that this is not feasible to do this by using the internal descriptor controller.