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RamaMohan's avatar
RamaMohan
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7 years ago

Does wr_dma interface of AVMM DMA descriptor controller support pipelined reads from application interface in A10

Hi, We have a use case where we wanted to use the Descriptor controller of A10 AVMM DMA with pipelined accesses on Write DMA Avalon-MM Master port. Actually we need a huge delay to respond with the ...
RamaMohan's avatar
RamaMohan
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Yes, I'm referring specifically to the the PCIe AVMM DMA pointed by you(Arria10). We are using version 17.1 of the Platform Designer.

Thanks,

RamaMohan