Forum Discussion
RamaMohan
Occasional Contributor
Occasional ContributorDoes wr_dma interface of AVMM DMA descriptor controller support pipelined reads from application interface in A10
Hi, We have a use case where we wanted to use the Descriptor controller of A10 AVMM DMA with pipelined accesses on Write DMA Avalon-MM Master port. Actually we need a huge delay to respond with the ...
GuaBin_N_Intel
Contributor
ContributorThere are few different DMA IPs in the Platform designer. Are you referring to this PCIE specific https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avmm_dma.pdf?
