Forum Discussion
New ContributorDoes the Stratix 10 Mailbox Client IP automatically send a Flash write enable command before a QSPI_WRITE or QSPI_ERASE command?
Hi Craig May,
Yes, the IP will automatically do write enable for all the command that require write enable.
Regards,
YL
Regular ContributorHi Craig,
Yes, you are right. You will need to check the Interupt Status Register status before you proceed for the next write command.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20087.pdf (Page 11)
Regards,
YL
- CMay01
I am not asking about the ISR. I am referring to the write enable in a flash memory device that must be set before performing a write or erase to that device. The rsu1.tcl script pointed to in the document you link to (https://www.intel.com/content/dam/altera-www/global/en_US/others/support/devices/configuration/rsu1.tcl) does not seem to send the write enable command, hence my original question.
