Does the Intel FPGA Avalon I2C (Master) Core issue a STOP after receiving a NACK? If not, how can just a STOP be issued without transmitiing any data.

Hi Bill,

If you follow the link [1] drives you to page 178 with some examples of transmitting or receiving data.

Also, you can see more information about the protocol, specifically NACK on the link [2] on page 5.

[1]https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_embedded_ip.pdf#page=178

[2] http://www.ti.com/lit/an/slva704/slva704.pdf