Does the Intel FPGA Avalon I2C (Master) Core issue a STOP after receiving a NACK? If not, how can just a STOP be issued without transmitiing any data.

If the I2C Master Core gets a NACK when the device address is transmitted, how does it behave? Does it just set the MAK bit in the ISR? Does it issue a STOP? Does the driver need to issue the STOP or a repeated START?