Does the Intel FPGA Avalon I2C (Master) Core issue a STOP after receiving a NACK? If not, how can just a STOP be issued without transmitiing any data.

Hello Bill.

I'm seeing at the link [1] that you get a NACK or Stop condition after transfer data.

Could you please elaborate more what you need. The guide of the Avalon I2C below for more information.

[1] https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_embedded_ip.pdf#page=175

Best regards.

Isaac