DMA read using PCIe hard core

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do you know some Doc about the PCIe DMA using Altera hard IP, especially the DMA read.

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Sorry I do not.

I analyzed the Altera Qsys PCIe end-point design in this thread:

http://www.alteraforum.com/forum/showthread.php?t=35678

but the end-point bus master interface was not suitable for my application. Rather than spend time to develop my own PCIe IP at the TLP level I used a PowerPC processor with PCIe for my PCIe interface and put the FPGA on its local bus.

I'd recommend looking at whether Altera has PCIe simulation support now, and if they do not, post a new thread asking people to recommend PCIe simulation IP from a third party.

Cheers,

Dave