DMA Controller is not stopping!!!

That knowledge database solution is saying that if you enable say 32, 16, and 8 bit transfers in the hardware but enable bursting then you can only perform 32-bit transfers. I also seem to recall an old bug where if you set the burst length to 128 for example then that was the maximum transfer (in beats) that you could perform as well. Hopefully that has been fixed but I haven't used that DMA in years so I can't be certain.

I typically use the mSGDMA that I developed years ago which is offered in Qsys starting in 14.0. Unfortunately the official driver has not been included with the IP yet so you can find it here if you want to switch to a different DMA: http://www.alterawiki.com/wiki/modular_sgdma The programming model for the mSGDMA is similar to how you are bit banging the registers but I give you baremetal APIs to hide those details. One of these days I'll create a frontend for the mSGDMA to make it behave like the old DMA core that you are currently using but I haven't found the time to do so.