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JoEl's avatar
JoEl
Icon for Occasional Contributor rankOccasional Contributor
7 years ago
Solved

DisplayPort_TX IP in image video mode

Hi all, I am working on transfer from classic DisplayPort video interface with Hsync, Vsync and DE to video image interface. Reason to switch is suport of adaptive synfchronization which should be ...
  • JoEl's avatar
    JoEl
    7 years ago

    Hi guys,

    Finall answer on whats wrong with picture (protocol)at top is video valid signal. It have to be zero in blanking, and it have to be valid when eol, eof, sof and sol occur.

JoEl's avatar
JoEl
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Hi all,

problem with video_im_interface was caused by using clock_enble from our interface to drive video_im_valid. This signal stays valid even in blanking which cause endless data stream to dp_tx. This bug invoke interface training every few clock cycles. With video_im_valid correction - during blanking (bitwise & with data_enable), it seems to be correct with internal HDL signal generator.

With HDMI source from outside with more variable clock_enable signal (caused by oversampling of HDMI) signal is not able to measure input parameters so there are no output clock / data, but link was established.

Q: Is it problem to use clock enable like we have it in picture below ?

point to think about: I agree that we should have valid pixel when eol/eof occur - can it be problem?

Thank you,

JoEl