Occasional ContributorHi guys,
Finall answer on whats wrong with picture (protocol)at top is video valid signal. It have to be zero in blanking, and it have to be valid when eol, eof, sof and sol occur.
Occasional ContributorHi all,
problem with video_im_interface was caused by using clock_enble from our interface to drive video_im_valid. This signal stays valid even in blanking which cause endless data stream to dp_tx. This bug invoke interface training every few clock cycles. With video_im_valid correction - during blanking (bitwise & with data_enable), it seems to be correct with internal HDL signal generator.
With HDMI source from outside with more variable clock_enable signal (caused by oversampling of HDMI) signal is not able to measure input parameters so there are no output clock / data, but link was established.
Q: Is it problem to use clock enable like we have it in picture below ?
point to think about: I agree that we should have valid pixel when eol/eof occur - can it be problem?
Thank you,
JoEl
