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JoEl's avatar
JoEl
Icon for Occasional Contributor rankOccasional Contributor
7 years ago
Solved

DisplayPort_TX IP in image video mode

Hi all, I am working on transfer from classic DisplayPort video interface with Hsync, Vsync and DE to video image interface. Reason to switch is suport of adaptive synfchronization which should be ...
  • JoEl's avatar
    JoEl
    7 years ago

    Hi guys,

    Finall answer on whats wrong with picture (protocol)at top is video valid signal. It have to be zero in blanking, and it have to be valid when eol, eof, sof and sol occur.

Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago
Hi Josef, Can you help to clarify few things below so that I can help you better. 1) May I know which Intel FPGA that you are referring here ? is it Arria 10 or other FPGA family ? 2) Are you using Quartus Standard edition or Pro edition ? Which Quartus revision to be exact ? 3) Is this Display Port Tx only design or Display port Rx loopback to Tx design ? 4) Are you running the testing with your own design or using Display Port example design ? Thanks. Regards, dlim