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watari's avatar
watari
Icon for New Contributor rankNew Contributor
7 years ago

DisplayPort Rx IP can't generate stable recover clock in clock recover module.

Hi community member We'd like to use DP Rx IP as eDP Rx and generate stable recover clock by bitec_clkrec module. We already implemented it into Arria V (5AGXMB3G4F31I3N) which was referred example...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Hi Sir,

Is the PLL integrate in the example design or you generate it externally?

If it is integrate in the example design, I don't think it is recommend to change the frequency.

If it is generate externally, I will suggest you to refer to PLL user guide to determine the parameters.

Also, refer to Arria V Errata sheet to check it there a known issue that impact PLL with certain frequency range.