DisplayPort IP Sink - Spread Spectrum Clocking

Are you looking at the Bitech Displayport IP core.

I don't know for sure, but this should be more of a function of the FPGA PLL than the logic core. Basically can the core PLL maintain lock when the input clock is spread.

I would check the specific family of FPGA handbook and check the PLL capablilites. I know SATA also can use spread spectrum clocking, and some families for FPGA are ok with this while others are not.

Pete