Forum Discussion

DZuck1's avatar
DZuck1
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

DisplayPort IP Example Design - VHDL

Hi, I am trying to use Quartus Prime 17.0 to generate the DisplayPort IP Example Design for VHDL simulation. I followed through the directions in the UG (https://www.intel.com/content/dam/www/progr...
Vicky1's avatar
Vicky1
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi Daniel,

Yes, It supports for vhdl & verilog but presently available in verilog only.

Regards,

Vikas