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DZuck1
Occasional Contributor
Occasional ContributorDisplayPort IP Example Design - VHDL
Hi, I am trying to use Quartus Prime 17.0 to generate the DisplayPort IP Example Design for VHDL simulation. I followed through the directions in the UG (https://www.intel.com/content/dam/www/progr...
DZuck1Occasional Contributor
Occasional ContributorHi Vikas,
It looks like Verilog is the only one supported based on Figure 2 and Table 1 but Table 21 says that VHDL is supported.
Thanks,
Daniel
