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CSegu's avatar
CSegu
Icon for New Contributor rankNew Contributor
7 years ago

Dear Sir, I am using ALTLVDS_RX IP on a Cyclone V GX device, and noticing that for some reason the rx_locked pin of PLL is never being locked. Same problem noticed when PLL is set to shared between LVDS transmitter and receiver. DPA not active.

I am using ALTLVDS_RX IP on a Cyclone V GX device, and noticing that for some reason the rx_locked pin of PLL is never being locked. Same problem noticed is PLL is set to shared between transmitter a...
Rahul_S_Intel1's avatar
Rahul_S_Intel1
Icon for Frequent Contributor rankFrequent Contributor
7 years ago
Hi, I am requesting to isolate the problem first, First make a simple LVDS Rx and requesting you to signal tap the signals. If still lock signal is not high, I am requesting to check the input to the clock ,is there any noise is been affected.
CSegu's avatar
CSegu
Icon for New Contributor rankNew Contributor
7 years ago
Dear RSree, Now I am having rx_clock and tx_clock pins are locked high now. I went to check with oscilloscope for the LVDS transmitter output clock tx_outclock but this is not being generated. Why tx_outclock is not being generated? Regards, Clive