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WOver1
New Contributor
New ContributorDDR3 SDRAM UniPHY larger than expected latency
The UniPHY (v16.1) DDR3 SDRAM controller in my Stratix V design a shows much larger than expected latency. The DDR3 refresh is not user controlled. Largest read latency so far observed is around 185...
WOver1New Contributor
New ContributorThis does not explain latency of up to around 2000 cycles for one command every 15 to 60ms apart, right?
