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WOver1
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7 years ago

DDR3 SDRAM UniPHY larger than expected latency

The UniPHY (v16.1) DDR3 SDRAM controller in my Stratix V design a shows much larger than expected latency. The DDR3 refresh is not user controlled. Largest read latency so far observed is around 185...
WOver1's avatar
WOver1
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7 years ago

The last reference is about how to get a few cycles off on the average latency. The average latency is as expected, so that is fine. However at 50ms intervals (in that order) i see a latency which is about 100 times larger than average. This is a problem in my design. I wonder where this comes from. Refresh interval is in this order (32ms / 64ms), but should not take this long.

I`m not looking for a way reduce the average latency with 1 or 2 cycles, but i want to understand where the very high max latency comes from.