DDR2 User Controlled Refresh

Hi,

Thanks for your answers. I could do the user controlled refresh on DDR2. But, now struck with another problem.

We know that DDR memories work in a burst fashion. To describe in detail, check my settings in the images attached.

1) I use the same data bit width, 32, for DDR2 HPC II local interface as well as the master connected to it.

2) In the full rate mode both operate at the same frequency of 125 MHz.

3) Number of DQs = 16. "memory Burst Length = 4" and "Maximum Local Interface Burst = 8".

4) You can see in the image SOPC.bmp that I try to access the DDR2 from a component called tt_shared_ddr2. The component simply connects the instruction and data cache of the CPU (32 byte cache line, 32 byte burst) to the DDR2.

5) For each "cache miss" burst of 8 is asked to the tt_shared_ddr2, which is simply forwarded to the DDR2.

6) I tried both address mapings "chip-bank-row-col" and "chip-row-bank-col".

now my question:

When the data is asked in a burst fashion, the responce is only word by word. And there are >32 clock cycles between two "read_data_valid".

According to the documentation, 16 bit DQs * 4 Beat burst = 64 bits of data. And that makes 2 "read_data_valid" back-to-back. I am using cyclone III development kit.

Best regards,

Hardik Shah