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Altera_Forum
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14 years ago

DDR2 User Controlled Refresh

Hi, My name is Hardik Shah. I am using Cyc3 Dev board for my work. I have the following questions. I am using high performance controller. i) The document "External Memory Interface H...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Hi std_logic,

Thanks for the information. The JEDEC specification says, "When CS, RAS and CAS are held LOW and WE HIGH at the rising edge of the clock, the chip enters the Refresh mode (REF)."

(1) Is there any internal logic which supplies with the ROW numbers and informs the memory which ROW to refresh?

(2) If yes, is there any way to control which ROW to refresh from outside? Though we have 8192 ROWs, we wont use them all. So only those ROWs are required to refresh which contain data.

Best regards,

Hardik