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Honored Contributor
Honored ContributorDDR2 SDRAM with UniPHY not generating half_rate_clock
Hi there, I'm using Quartus 12.1 SP1 and generated a DDR2 SDRAM Controller with UniPHY via the MegaWizard Plugin Manager. The Memory Frequency is 400 MHz, PLL reference clock 50 MHz and the Rate...
Altera_ForumHonored Contributor
Honored ContributorFWIW, I think I see that this happens because of generated code as follows; seems to be independent of half-rate / full-rate controller setting.
In <instance>/synthesis/submodules/<instance>_mem_if_ddr2_emif_pll0.sv we have some assignments. assign afi_clk = pll_afi_clk; assign afi_half_clk = 1'b0; This is service request 10945983.
